NAND read disturb and program interference: mechanisms and qualification

Reading flash sounds non-destructive: no host write command was issued, so the stored state should remain untouched. At the logical interface that is the intended abstraction. At the NAND array, however, reading one cell requires voltages on other cells, and programming one cell creates electric coupling to its neighbors. Small analog effects can accumulate until digital decisions become less reliable.

This article separates two mechanisms—read disturb and program interference—and turns them into a qualification method. It does not provide a universal read-count limit. Such a number would be technically invalid without an exact NAND generation, architecture, state, wear level and controller policy.

The cell stores an analog state

NAND encodes data as threshold-voltage windows. SLC uses two nominal states; MLC, TLC and QLC use 4, 8 and 16. More states divide the usable voltage range into narrower windows, so smaller shifts or broadening can cross a read boundary.

A read applies one or more reference voltages to the selected wordline. Cells on unselected wordlines in the same series string must conduct so the sense amplifier can observe the selected cell. The device therefore applies a pass-through voltage (Vpass) to those unselected wordlines.

A program operation uses incremental voltage pulses and verify steps to move selected cells into their target distributions. Electric coupling means the operation is not perfectly isolated from neighboring cells.

The logical bit is discrete; the physical state and its margin are continuous.

Read disturb: observation creates stress

During a read, Vpass is high enough to turn on unselected cells regardless of their stored state. It is below a normal program condition, but repeated application can produce a small cumulative threshold shift. The affected page may be one that the host did not request; spatial locality is defined by the physical NAND block/string, not the filesystem name.

Cai et al. experimentally characterized 2Y-nm planar MLC NAND and found that read-disturb effects increased with repeated reads, P/E wear and pass-through voltage [1]. They also showed state-dependent susceptibility and proposed per-block voltage tuning. These findings establish a mechanism and experimental method. Their reported read counts and lifetime gains are not specifications for modern 3D TLC/QLC.

The workload pattern that matters is many reads to hot data sharing physical locality with cold data. Examples can include boot assets, indexes, model weights, lookup tables or database metadata repeatedly read while adjacent mapped pages are rarely rewritten.

Program interference: a neighboring write moves the boundary

Program interference occurs when programming a cell shifts the threshold voltage of another cell through parasitic coupling. The magnitude depends on relative position, victim and aggressor state, programming sequence, geometry and process technology.

Cai et al. measured interference in planar MLC and modeled how a neighboring program operation changes the victim distribution [2]. Neighbor-cell assisted correction then used information about adjacent-cell values to choose better read decisions [3]. Again, the insight is transferable; the quantitative coupling coefficients are not universal.

Programming order matters because a victim written earlier can be disturbed when a neighboring wordline is programmed later. NAND vendors and controllers define sequences and algorithms to manage this. A raw-NAND host must not invent a page-program order from generic knowledge; it must follow the exact device specification.

Distinguish the mechanisms

Real devices combine them. Wear can increase disturb sensitivity; retention can move a distribution closer to a boundary before disturb; read retry can recover a weak page but increase latency; successful recovery may trigger refresh and new internal writes [4].

Do not diagnose from one symptom. A checksum failure after a read-heavy test could also come from interface signal integrity, power instability, software addressing, DRAM corruption or an unsafe program sequence.

Managed flash changes what the host can see

SSD, eMMC, UFS and memory-card controllers can use several mitigations:

• track read activity by block or region;
• adapt Vpass or read-reference voltages;
• correct errors with ECC and read retry;
• copy data to a fresh block before margin is exhausted;
• retire blocks and update logical-to-physical mapping;
• use parity across dies/pages for recovery.

KIOXIA describes refresh in managed flash as scanning or detecting at-risk blocks and rewriting recovered data to healthier blocks, while noting that implementation varies by manufacturer [5]. Micron's NAND guidance similarly recommends refresh to mitigate repeated-read disturb and requires correct ECC, operation-status checking and block retirement [6].

These mechanisms are valuable, but not free. Scanning and rewriting consume bandwidth, spare area and P/E cycles. A read-hot workload can therefore create background writes and long-tail latency even when the host issued no writes. Firmware policy is part of the storage product.

Design a mechanism-focused experiment

For raw NAND characterization, the laboratory needs physical block/page control and access to raw data before ECC. For managed devices, the controller hides placement, so the result is system-level evidence rather than a clean isolation of the physical mechanism.

1. Define sample strata

Include multiple units and lots, then separate at least:

• fresh and endurance-conditioned populations;
• short and aged retention intervals;
• relevant low, nominal and high device temperatures;
• data patterns and page types identified by the supplier;
• exact firmware and capacity configurations.

Avoid changing two stress variables without controls. If wear and retention both change, you cannot attribute the result to read disturb alone.

2. Create aggressor and victim data

Use versioned pseudorandom data with checksums. In raw NAND, place selected aggressor pages and victim pages in known physical relationships. Include control victims in blocks not exposed to the repeated-read workload.

In a managed SSD, logical addresses do not guarantee physical adjacency. You can still build a high-read working set plus a larger cold-data population, but describe the test as a black-box workload. Do not claim that one logical neighbor was one physical wordline away.

3. Preserve intermediate observations

At logarithmic checkpoints—for example after increasing read-count decades—capture:

• first-read raw data or the earliest host-visible read;
• corrected-error information, if exposed;
• retry depth or read latency distribution;
• device health and block-retirement changes;
• full victim-data checksums;
• temperature, power and workload counters.

Repeated verification reads are themselves part of the stress. Use separate sample groups or account for measurement-induced reads. Decide whether the objective is time to first correction growth, time to refresh, or time to user-data failure.

4. Exercise program patterns separately

For program interference on raw NAND, vary aggressor/victim states and follow supplier-approved program order. Capture victim distributions or raw errors before and after the aggressor operation. Managed devices generally do not expose enough placement control to claim a direct program-interference measurement; use supplier characterization plus end-to-end qualification.

5. Test recovery and power interruption

If the device refreshes data, measure foreground latency during recovery and verify data after the operation. Add controlled power interruptions only through an appropriate fixture and only after defining the expected atomicity. A controller that detects a weak page but loses mapping metadata during an interruption has traded one risk for another.

Report distributions, not a single pass point

A report should contain:

Zero failures in a small test does not prove zero field risk. If no user mismatch occurs but correction and retry increase, report that trend rather than flattening the result into “pass.” If a refreshed managed device remains correct, state that the complete controller policy passed the workload; do not infer that the underlying NAND showed no disturb.

Turn the lesson into a product requirement

A useful requirement is conditional and observable:

The proposed configuration shall preserve end-to-end data integrity under the specified read-hot/cold-data workload after defined wear and retention conditioning. Supplier shall identify applicable read-disturb, refresh/read-reclaim and uncorrectable-error behavior, including available telemetry and firmware dependencies. Qualification shall record latency distributions, recovery events and data mismatches. Changes to NAND, controller or firmware require notification and impact review.

For raw NAND, add device-specific program sequence, maximum use-condition guidance, ECC/codeword requirement, read-retry controls and bad-block retirement procedure. For managed products, ask the supplier to explain what host activity enables background refresh and whether a full logical read actually causes at-risk data to be relocated.

Limits and modern 3D NAND

The cited public experiments are unusually valuable because they expose raw threshold distributions and controlled physical locations. Most used planar MLC devices. Vertical 3D NAND changes cell geometry, layer variation, coupling paths, algorithms and error populations; TLC and QLC add more state boundaries. Vendor controllers also evolve.

It is sound to carry forward these principles:

• reading can stress unselected cells;
• programming can shift neighboring states;
• error mechanisms interact with wear and retention;
• adaptive sensing, ECC and refresh trade error margin for latency and writes;
• qualification must preserve physical and statistical context.

It is unsound to copy a paper's read-count threshold or coupling coefficient into a modern product specification without supplier correlation.

Bottom line

Read disturb and program interference are not reasons to distrust NAND; they are reasons to treat NAND as an analog medium behind a digital contract. The controller's job is to keep those effects below the user-visible boundary through sensing, ECC, retry, refresh and retirement. The engineer's job is to test that contract under the actual mission profile and to state what the test could not observe.

Use this method with the deeper RBER/UBER and LDPC guide, retention qualification and the site's OEM qualification plan.